Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate. In a flash memory, erased cells have a low threshold voltage, and are conductive. Erased cells are said to have a logic “1” value. programmed cells have a higher threshold voltage, are less conductive, and are said to have a logic “0” value. Programming and erasing of typical flash memory cells will not be described further herein.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bitline. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bitline.
Memories such as those described herein are subject to failure of components due to any number of factors. Therefore, redundancies are typically built in to memories, to allow for operation even if some of the components fail. Redundancies in memory devices allow for the invalidation of faulty bitlines and the moving of data to a redundant area of the array. Once a bitline is faulty, it is a waste of valuable power to continue operations on that bitline.
In a program operation of a page/row of the memory array, after the data is programmed to the array, it is typically immediately read again from memory array so that the data can be verified. In this verification, the data that was programmed in the memory array is compared with the original data typically still being held in the I/O buffer or data cache to discover any errors and ensure it was properly programmed. If an error is discovered, the location is typically invalidated and the data moved to a new location to be programmed into the array once again.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved power management in memories.